SHAHRIYAR HOMEPAGE WEB PROJECT
FROM
November
2017
TO
December
2017
DRSVR Consolidated, Newport Beach, California, United States

A dynamic homepage website template with the site management tool. This template is designed for people with academic background and give them the ability to add their experiences dynamically to the website by using the provided site management tool.

Course Title: Personal

 

CSS HTML JAVASCRIPT PHP  Web Design 

Overnite Website Project
FROM
September
2017
TO
November
2017
University of California, Riverside, California, United States

Overnite is a dynamic website to help customers to find adventures in faraway places or your hometown, and access unique homes, experiences, and places around the world. Book everything your trip needs, or start earning money as a host. As a traveler, you can book homes, message your host and get directions to your home. As a host, you can share your extra space, message guests and manage their reservations.

Course Title: Introduction to Software Engineering

 

CSS HTML JAVASCRIPT PHP  Web Design 

Data Analyzer
FROM
June
2017
TO
July
2017
DRSVR Consolidated, Newport Beach, California, United States

I have implemented the DRSVR Data Analyzer in python to help me process my simulation outputs. This data analyzer will parse the result files, analyze them and automatically generate a graph.

Course Title: Personal

 

Python 

High Performance Computing Mini Projects
FROM
September
2016
TO
December
2016
University of California, Riverside, California, United States

These three mini-projects cover High-Performance Computing on multicore shared memory computers and on distributed memory computing clusters. In these projects, we have used Message Passing Interface(MPI) parallel file systems and the C language. In the project 1 and project 2, we have implemented a version of matrix multiplication to take into account register reuse to improve performance. In the third project, the goal was to use the sieve of Eratosthenes for determining the prime numbers in a very large interval and study how different modifications affect the performance. We will use parallel programming to divide the work among different cores and nodes.

Course Title: High Performance Computing

  

C++  High Performance Computing MPI 

LLVM Compiler Block and Edge Profiling
FROM
March
2016
TO
April
2016
University of California, Riverside, California, United States

Modified LLVM to profile an arbitrary program written in C++ for number of basic blocks, edges and loops.

Course Title: Compiler Construction

 

C++  Compiler LLVM  Software Engineering 

Trace-Driven Cache Simulator
FROM
February
2016
TO
March
2016
University of California, Riverside, California, United States

In this project, we have implemented the Trace-Driven Cache Simulator. This runs the cache simulation based on the provided trace and config files. This simulator supports Fully Associative, Set-Associative, and Direct Mapped caches. Also, we support random, LRU and FIFO replacement policies.

Course Title: Advanced Computer Architecture

  

Computer Architecture JAVA  Simulation 

XV6 Operating System Mini Projects
FROM
February
2016
TO
April
2016
University of California, Riverside, California, United States

Xv6 is a teaching operating system developed in the summer of 2006 for MIT's operating systems course. In this project, we have implemented three mini-projects to learn about different aspects of the operating system. In the first project, we have implemented a new system call and a lottery scheduler; in the second project, we add support for handling the null pointer in the Xv6. In the final project, we added the multithreading to the Xv6 that supports the Spinlock and the Queue-based lock.

Course Title: Advanced Operating System

  

Operating System  Simulation  Software Engineering 

Two-level Warp Scheduling Utilizing Dynamic Warps
FROM
September
2015
TO
December
2015
University of California, Riverside, California, United States

Warp scheduling is a vital stage in a GPU’s execution cycle. Since the program counter for all warps differ, the scheduler needs to take into account the number of available resources and ready operands before issuing the instruction to one of the execution units. In recent years, with the rise of GPGPU’s popularity, numerous attempts have been made to improve the scheduling process, such as dynamic warps, more complex scheduling queues and hiding memory access latencies. In this project, we have used dynamic warps and two-level round robin scheduling. There are still many improvement possibilities in warp scheduling which can positively affect performance and power consumption, and we look forward to exploring them more in the near future.

Course Title: GPU Architecture and Parallel Programming

  

C++  Computer Architecture CUDA  Simulation 

Nvidia CUDA Mini Projects
FROM
September
2015
TO
December
2015
University of California, Riverside, California, United States

CUDA is a parallel computing platform and application programming interface model created by Nvidia. We have implemented four mini-project to learn basics of CUDA programming model.

     
     
     
     

Course Title: GPU Architecture and Parallel Programming

  

Computer Architecture CUDA 

Sharif Tachometer
FROM
June
2014
TO
August
2014
Sharif University of Technology, Tehran, Iran

In this project, we designed and build a digital tachometer that measures the working speed of an engine in revolutions per minute by using a light sensor and shows it on the LCD screen, furthermore, it can send data directly to a computer for further analysis by using a serial port.

Course Title: Computer Hardware Lab

 

Altium Designer  Digital System Design  Proteus 

Computer Networks Labs
FROM
January
2014
TO
May
2014
Sharif University of Technology, Tehran, Iran

In the computer architecture lab, we have learned to simulate a computer network using Cisco Packet Tracer.

     
     
     
     
     
     
     
     
     
     

Course Title: Computer Networks

 

Cisco Packet Tracer  Computer Networks  Simulation 

Implementation of an Arithmetic core from RTL to ASIC Layout
FROM
December
2013
TO
January
2014
Sharif University of Technology, Tehran, Iran

In this project, we designed an arithmetic code in Verilog language and test the functionality of it by running benchmarks in the Modelsim program. Then we used a Design Compiler application to synthesis our code to a specific library under area and power constraints. Then we used power compiler application to analyze the power of our design. Then we used a SOC-Encounter application to place and route our synthesized design; Finally, we did RC-Extraction and completed the DRC and P&R of our final layout.
This project was very interesting because after doing this project I can claim that I have the ability to design the complete computer system from the highest to the lowest level.

Course Title: VLSI Design

 

Design Compiler  Digital System Design  Hspice  Model Sim  Power Compiler  S O C Encounter 

Implementation of a Mini-C Compiler
FROM
September
2013
TO
January
2014
Sharif University of Technology, Tehran, Iran

In this project, we have implemented a compiler for a simplified C language in java to learn basic concepts of a compiler design. This project was one of the most difficult projects that I have ever done.

     
     
     
     
     


Course Title: Compiler Design

Compiler JAVA 

Multipattern LED Runner
FROM
January
2013
TO
May
2013
Sharif University of Technology, Tehran, Iran

In this project, we have implemented a Multi-Pattern LED Runner by using a Microcontroller in the Proteus application.

Course Title: Microcontrollers

 

Altium Designer  Proteus 

Implementation of a Least Slack Time Rate First Scheduler in the FreeBSD OS
FROM
September
2012
TO
January
2013
Sharif University of Technology, Tehran, Iran

In this project, we have added a Least Slack Time Rate First Scheduler by hacking the FreeBSD kernel.

Course Title: Operating System

Operating System 

Implementation of a Single-Cycle Pipeline Processor
FROM
January
2012
TO
May
2012
Sharif University of Technology, Tehran, Iran

In this program, we have implemented a Single Cycle Pipeline MIPS Processor in Verilog to get better understanding about hidden details of a computer architecture that needs a lot of attention.

Course Title: Computer Architecture

Computer Architecture  Verilog 

Implementation of a Queen Graph Generator
FROM
September
2011
TO
January
2012
Sharif University of Technology, Tehran, Iran

In this project, I have implemented a mathematical problem of a queen graph in java just for fun.

Course Title: Design of Algorithms

JAVA 

Implementation of an Elevator Simulator
FROM
January
2010
TO
May
2010
Sharif University of Technology, Tehran, Iran

In this project, I have implemented a simple elevator simulator in C++ as a course project to examine our programming skills.

Course Title: Advanced Programming Languages

C++  Software Engineering